VTIL

Initial page
Github
Instruction Set
- General Information
- Data movement
  - MOV
  - MOVSX
  - STR
  - LDD
- Arithmetic
  - NEG
  - ADD
  - SUB
  - MUL
  - MULHI
  - IMUL
  - IMULHI
  - DIV
  - IDIV
  - REM
  - IREM
- Bitwise
  - POPCNT
  - BSF
  - BSR
  - NOT
  - SHR
  - SHL
  - XOR
  - OR
  - AND
  - ROR
  - ROL
- Conditionals
  - TG
  - TGE
  - TE
  - TNE
  - TL
  - TLE
  - TUG
  - TUGE
  - TUL
  - TULE
  - IFS
- Control Flow
  - JS
  - JMP
  - VEXIT
  - VXCALL
- Special Instructions

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BSR

Instruction

Operand 1

Description

BSR

Reg

OP1 = OP1 ? BitScanReverse OP1 + 1 : 0

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Last updated 3 years ago

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